1. Field of the Invention
The present invention relates generally to a method and a system for analyzing defects in semiconductors. In particular, the present invention relates to a method of calculating the probability of failures caused by defects, a method of calculating a defect limited yield, and a system for calculating the probability of failures caused by defects.
2. Description of the Related Art
Several hundreds or millions of semiconductor chips are now mounted on a single wafer due to the extensive development of manufacturing techniques of semiconductor integrated circuits. As a result, the analysis of defects or electrical defects occurring during the integration of semiconductor chips is a step in the process of manufacturing semiconductors. Thus, defect analysis techniques to determine defects in semiconductors have been rapidly developed.
There are numerous methods of analyzing defects; however, most defects are measured by defect inspectors. The inspectors determine the presence of foreign materials on a semiconductor wafer, analyze defect data according to number, location, etc., and measure the electrical characteristics of semiconductor devices. Methods of analyzing defects using the probability of failures due to defects are well-known.
In a conventional method of calculating the probability of failures caused by defects, the probability of failures caused by the defects is measured in each of the inspected blocks of a wafer chip or in each of the wafer chips. As shown in FIG. 1, blocks 10 are inspected to determine whether defects D and/or failures F occur in inspected blocks 10. The inspection is performed in each of the chips of a wafer by general defect and failure detection equipment. In particular, a number N1 of the inspected blocks having the defects D in which the failures F occur, i.e., block 10-1, and a number N2 of inspected blocks in which failures F do not occur, i.e., block 10-2 are determined.
The probability of failures caused by the defects D, i.e., a hit ratio, is calculated using N1 and N2. In particular, the hit ratio is defined as a ratio of the number N1 of the inspected blocks having failures F caused by defects D to the sum (N1+N2) of the number N1 of the inspected blocks having failures F caused by defects D and the number N2 of the inspected blocks not having failures F caused by defects D, as illustrated in formula (1).HR(Hit Ratio)=N1/(N1+N2)  (1)
A conventional hit ratio in each of the wafer chips is calculated by the following method. First, the number of defects is measured in each of the wafer chips using defect detection equipment. Next, if the number of defects is over a desired number, it is determined that the wafer chips fail. On the other hand, if the number of defects is below the desired number, it is determined that the wafer chips are good.
However, the conventional hit ratio has numerous problems. First, the number N1 of inspected blocks having defects in which failures occur includes the number of failures caused by defects and the number of failures caused by reasons other than defects. Thus, since the conventional hit ratio includes probabilities of failures caused by the defects as well as other causes, the conventional hit ratio does not reflect the probability of the failures caused by defects only.
Second, a hit ratio in each of the wafer chips identifies a good or bad state of the wafer chips using only the number of defects. However, if the defects are concentrated in only certain regions, the defects may have a fatal effect on the chips even though the number of the defects is small. In addition, even though the number of the defects is large, the defects may be disposed at large intervals and may not cause the failure of the wafer chips. Thus, it is inaccurate to measure a yield using the number of defects in the wafer chips.